1. Field of the Invention
The present invention generally relates to mitigation of interconnect variability of an integrated circuit (“chip”). Specifically, the present invention provides a way to mitigate interconnect variability of a chip during its design stage.
2. Related Art
In nanometer-scale Very Large-Scale Integration (VLSI), the design of a chip is increasingly affected by the variability in the back end of the line (BEOL), or interconnect resistance and capacitance. The mismatch between design and manufacturing has to be well controlled in order to guarantee performance and manufacturability. Chemical-Mechanical Polishing (CMP) is widely used as a primary technique in modern integrated circuit fabrication. In this process, after depositing one layer of material on previous layers of material along with an insulating dielectric, CMP is used to planarize the surface layer. Global planarization is typically necessary for establishing reliable multilevel copper interconnects. On the other hand, CMP planarization is not only affected by the manufacturing process, but also it is related to the design itself Experimental results show that metal thickness is closely related to the metal density of the design layout.
To reduce the metal density variation so as to help produce a more flattened layout, two techniques are widely used. Under one technique, “dummy fills”, which are tiny metal squares or rectangles, are inserted in low density regions to equalize the spatial density. Under the second technique, holes are formed (i.e., known as “cheesing”) on wide wires in order to reduce the metal density. However, both techniques are applied in the post-design process. Although these techniques can improve the layout density evenness, the introduction of millions of dummy fills and cheese holes may affect interconnect signal delay and crosstalk due to the resistance and the coupling capacitance changes. More importantly, these post-design processes represent a more “passive” compensation since the design is fixed already. Only simple local changes can be applied, and the compensation is strictly constrained by the existing design. Moreover, it is highly likely that some regions in the layout cannot reach the required metal density even with dummy fills or cheesing holes. Still yet, if there are critical nets that traverse these regions, the wire thickness of these nets may be out of the design range due to the thickness loss/gain caused by the CMP process. As such, these nets may fail to meet the timing closure.
In view of the foregoing, there exists a need for an improved technique for mitigating interconnect variability. Specifically, a need exists for a technique that mitigates interconnect variability during the design stage of a chip to avoid the problems described above.